The present invention relates generally to integrated circuits, and specifically to probing pads used for testing purposes in integrated circuits.
Integrated circuits typically have input and output pads which are used in testing as the electrical contact points at which probes can be placed to monitor performance of the integrated circuit during test procedures. Typically, such pads do not have a perfectly flat surface, or may include solder irregularities, or bumps, which tend to prevent or interfere with obtaining a good, solid electrical connection between the probes and the pads.
This problem is even more pronounced in testing applications in which multiple probes are applied to a plurality of pads on a chip during automatic testing. In high density multi-chip packaging technology, electrical probing for bare chip AC testing, burn-in testing and substrate testing, before assembly of the integrated circuit package are required in order to enhance manufacturing yield. If good electrical contact between the probes and the pads is not made during testing, erroneous test results may be obtained with the consequent rejection of otherwise properly performing integrated circuits. The yield of a particular manufacturing run of the integrated circuit in question is thereby lowered which, in turn, increases the cost of the integrated circuits.
An additional desirable requirement is that testing use a temporary substrate which can be used to verify the electrical functionality of integrated circuit chips without any chemical bonding between the pad of the integrated circuit chip and the pad of the temporary substrate, such as, for example, in initial multi-chip module defining stages of production of bread boards in print wiring board packages. The temporary substrate so utilized can also be used during any rework processing performed on integrated circuit chips which did not function properly during such preliminary stages of manufacture. In this situation as well there is a need for testing devices which can accommodate normally occurring variations in the contact structure of integrated circuits being tested to enhance the output yield.